Our Lab offers:
- Electromigration (EM) testing on both die level and package level interconnects. Low stress currents, down to hundreds of nano-amperes are available for testing of the most advanced metal lines and vias. Capability of parallel testing at high currents, up to several amperes for far backend of the line interconnects such as wafer level chip scale package (WLCSP) solder balls, flip chip bumps, copper pillars and through silicon vias (TSV).
- Time Dependent Dielectric Breakdown (TDDB) testing of both BEoL and FEoL dielectrics. Voltages up the kilovolt range available for stressing of thick and robust dielectrics.
- Hot Carrier Injection (HCI) and High Temperature Reverse Bias (HTRB) testing on field effect transistor (FET) and bipolar junction transistors (BJT) at a wide range of voltage and current conditions. Low temperature oven and chuck options available for highly accelerated stress.
- Bias Temperature Instability (BTI) using high speed parallel source measurement units (SMU) with micro-second measurement speed for fast sweeps and on-the-fly (OTF) measurement.
- Silicon Photonics (SiPh) parallel stress and characterization capabilities including high current wafer level stress.
- Ring Oscillator (RO) circuit level reliability testing with frequency measurement capability.
- Both multi-site wafer level and package level reliability testing options for all applications, including high temperature wafer level electromigration.
- AC and pulsed DC stress and measurement capabilities for multiple applications.
- Experience with device level testing of Si, GaN, GaAs, SiC, InP.
- High temperatures available for accelerated stress of emerging materials such as Cobalt and Ruthenium.
- Turnkey package level reliability testing options, including wafer dicing, assembly, and testing.
- Design of experiment and test structure layout consulting.
- Comprehensive reports illustrated in full color graphs.
- Expert analysis and interpretation.