Our Lab offers:
- Electromigration (EM) Testing: Conducted on both die-level and package-level interconnects. We provide low-stress currents down to hundreds of nano-amperes for testing advanced metal lines and vias. We also offer parallel testing at high currents, up to several amperes, for far-backend-of-the-line interconnects, including wafer-level chip scale package (WLCSP) solder balls, flip chip bumps, copper pillars, and through-silicon vias (TSV).
- Time-Dependent Dielectric Breakdown (TDDB) Testing: Available for both BEoL and FEoL dielectrics, with voltages up to the kilovolt range for stressing thick and robust dielectrics.
- Hot Carrier Injection (HCI) and High-Temperature Reverse Bias (HTRB) Testing: Performed on field-effect transistors (FET) and bipolar junction transistors (BJT) under a wide range of voltage and current conditions. Low-temperature oven and chuck options are available for highly accelerated stress.
- Bias Temperature Instability (BTI) Testing: Utilizes high-speed parallel source measurement units (SMUs) with microsecond measurement speed for fast sweeps and on-the-fly (OTF) measurements.
- Silicon Photonics (SiPh) Testing: Includes parallel stress and characterization capabilities, with high-current wafer-level stress.
- Ring Oscillator (RO) Circuit-Level Reliability Testing: Includes frequency measurement capability.
- Multi-Site Reliability Testing: Available for both wafer-level and package-level applications, including high-temperature wafer-level electromigration testing.
- AC and Pulsed DC Stress and Measurement: Capabilities for multiple applications.
- Device-Level Testing Experience: Includes Si, GaN, GaAs, SiC, and InP.
- High-Temperature Testing: For accelerated stress of emerging materials such as Cobalt and Ruthenium.
- Turnkey Package-Level Reliability Testing: Includes wafer dicing, assembly, and testing.
- Design of Experiments and Test Structure Layout Consulting
- Comprehensive Reporting: Illustrated with full-color graphs.
- Expert Analysis and Interpretation